A metal-insulator (oxide)-semiconductor field effect transistor (MISFET or MOSFET) is a basic element of a semiconductor device. A complementary metal-oxide-semiconductor (CMOS) circuit to which the MOSFET is applied consumes less electricity, can easily achieve miniaturization and high integration, and can operate at a high speed, and therefore, the CMOS circuit is widely used as a device for constituting many LSIs.
In the past, a thermally-oxidized silicon (SiO2) film or a film obtained by nitriding oxidized silicon in heat or plasma (SiON) has been widely used for a gate insulating film of a MOSFET. An n-type polysilicon layer doped with phosphorus (P) or arsenic (As) and a p-type polysilicon layer doped with boron (B) have been widely used as a gate electrode.
However, according to the scaling law, when the gate insulating film is thinned, or the gate length is reduced, the gate leak current increases or the reliability decreases due to thinner film thickness of the SiO2 film or the SiON film. Since, e.g., the gate capacitance may decrease due to a depletion layer formed in the gate electrode, a method using an insulating material (high dielectric film) having a high dielectric constant for the gate insulating film and a method using a metal material for the gate electrode have been suggested.
Examples of high dielectric film materials include hafnium-based compounds and the like, and among them, hafnium oxide (HfO2) is a desired material since hafnium oxide can suppress degradation of the electron mobility and the hall mobility while it has a high dielectric constant. However, there is a problem in that characteristics degradation such as carrier mobility degradation may occur when high temperature treatment step such as activation annealing treatment of the source and the drain is performed.
Therefore, as compared with a conventional manufacturing method in which the high temperature treatment step of the source and the drain is applied after the gate insulating film and the gate electrode are formed, a manufacturing method in which the gate insulating film and the gate electrode are formed after the high temperature treatment is applied has been suggested. In this case, a transistor configuration formed according to the former manufacturing method will be referred to as a gate first structure, and a transistor configuration formed according to the latter manufacturing method will be referred to as a gate last structure.
For example, Patent Literature 1 discloses a CMOS circuit in which an n-channel MOSFET has a gate first structure, and a p-channel MOSFET has a gate last structure. In the CMOS circuit, first, both of the n-channel MOSFET and the p-channel MOSFET are formed in the gate first structure, and thereafter, the gate electrode is removed only in the p-channel MOSFET, and a new conductive layer is deposited to form a MOSFET having the gate last structure. In such process, by selecting a gate electrode material for each of them, a gate electrode having a work function (WF) appropriate for each of the n-channel MOSFET and the p-channel MOSFET can be formed.
When the gate electrode of the p-channel MOSFET having the gate last structure in the CMOS circuit disclosed in Patent Literature 1 is formed, first, a stopper film for chemical mechanical planarization (CMP) is formed, the gate electrode of the p-channel MOSFET having the gate first structure formed previously and the CMP stopper film on the gate electrode are removed, so that an opening portion is formed, and titanium nitride and aluminum are filled in the opening portion. Thereafter, excessive titanium nitride and aluminum film is polished and removed up to the CMP stopper film by the CMP step.
In the CMOS circuit of Patent Literature 1, a silicon nitride film (stress liner film) having pulling stress or compression stress is formed on the source and the drain, so that the stress of the channel region of the transistor is modulated, and the mobility of carriers is improved.
Patent Literature 2 discloses a method for planarizing a hard substrate surface such as SiC with CMP treatment, and thereafter, argon gas cluster emission and nitrogen gas cluster emission are applied to a substrate surface, thus removing polishing scratches made in the CMP treatment and planarizing the substrate surface.